1. Field of the Invention
The present invention relates to a synchronous acquisition circuit and a synchronous acquisition method of a spread spectrum code, in particular, to a synchronous acquisition circuit and a synchronous acquisition method of a direct sequence spread spectrum code. This is a counterpart of and claims priority to Japanese-Patent Application No. 2004-289781 filed on Oct. 1, 2004, which is herein incorporated by reference.
2. Description of the Related Art
FIG. 1 shows an instance of a digital code sequence which includes a plurality of the spread spectrum codes used in a direct sequence spread spectrum communication.
The spread spectrum codes as shown in FIG. 1 are cyclic shift type codes defined by a standard of IEEE 802.15.4 which is applied to an interface of a ZigBee physical layer. The ZigBee is a standard for a close-range radio communication which is executed in a 2.4 GHz Industrial Scientific Medical bandpass. Also, the digital code sequence is a pseudo random pattern, and the pseudo random pattern provides eight spread spectrum codes which are respectively composed of thirty-two chips, by cyclically shifting a starting location of the pseudo random pattern on 4-chip basis. Hereupon, each of the chips corresponds to a code of “0” or “1” and is equated with a “bit”. A plurality of symbols of “0” through “7” are assigned to respective ones of eight kinds of the spread code. As shown in FIG. 1, for example, the symbol “0” is assigned to the spread code which starts with “1101” and ends with “1110. ” Also, the symbol “7” is assigned to the spread code which starts with “1001” and ends with “1101.”
FIG. 2 is a circuit block diagram for describing a synchronous acquisition circuit of the spread spectrum code in the related art. The synchronous acquisition circuit includes a clock extracting circuit 1 and a code generating circuit 2. The clock extracting circuit 1 generates a clock signal CLK based on a signal IN which is output from a detection circuit of a radio receiver. The code generating circuit 2 converts the signal IN into a digital signal of “0” or “1” in accordance with the clock signal CLK, in order to generate the digital code sequence. The digital code sequence which is output from the code generating circuit 2 is provided to respective ones of eight correlation circuits 3-0 through 3-7. Each of the correlation circuits 3-0 through 3-7 corresponds to respective ones of the eight spread spectrum codes. The correlation circuits 3-0 through 3-7 check correlations between the digital code sequence and the spread spectrum codes in accordance with the clock signal CLK, in order to generate a plurality of correlation signals COR0 through COR7. The correlation signals COR0 through COR7 are provided to a demodulation circuit 4. The demodulation circuit 4 selects one of the correlation circuits 3-0 through 3-7 which generates a correlation signal which includes the greatest correlation value which exceeds a predetermined threshold correlation value when the demodulation circuit 4 receives a timing signal TIM, and then outputs one of symbols generated from the selected one of the correlation circuits 3-0 through 3-7 as a demodulation signal OUT.
Furthermore, the synchronous acquisition circuit includes a preamble detection circuit 5 and a set-reset type flip-flop circuit 6 in order to realize synchronization with respect to receiving radio communication signals. In actual radio communication, a specific pattern is prepended to transmit data of the radio communication signal as a preamble symbol. Hereupon, four consecutive spread spectrum codes of the symbol “0” are transmitted as the preamble symbol, prior to the transmit data. The preamble detection circuit 5 receives the correlation signal COR0 which is output from the correlation circuit 3-0. When the correlation signal COR0 has a correlation value which exceeds the predetermined threshold correlation value, the preamble detection circuit 5 generates a detection signal DET for a two-input AND circuit 7. The set-reset flip-flop circuit 6 has a set-terminal S which receives a reception starting signal ST which is indicative of starting a signal reception and has an output terminal coupled to an input terminal of the AND circuit 7. The AND circuit 7 generates an output signal S7 for a reset-terminal R of the set-reset flip-flop circuit 6 and a timing control circuit 8. The timing control circuit 8 counts a pulse number of the clock signal CLK, in order to generate the timing control signal TIM which has a width of one of the clock signal CLK every 32-chips which corresponds to a width of one of the symbols. The timing control circuit 8 starts counting the pulse number of the clock signal CLK when receiving the output signal S7 from the AND circuit 7.
Details of the operations with respect to the above-mentioned synchronous acquisition circuit are described below. When the set-reset flip-flop circuit 6 receives the reception starting signal ST, the set-reset flip-flop circuit 6 is set and then the. AND circuit 7 receives a signal of “1. ” On the other hand, the clock extracting circuit 1 and the code generating circuit 2 receives the signal IN from the detection circuit of the radio receiver at this time. The clock extracting circuit 1 generates the clock signal CLK based on the signal IN for the code generating circuit 2, the correlation circuits 3-0 through 3-7 and the timing control circuit 8. The signal IN is converted into the spread code, and then the spread code is provided to the eight correlation circuits 3-0 through 3-7. Thereafter, the correlation circuits 3-0 through 3-7 generate the correlation signals COR0 through COR7 for the demodulation circuit 4. The correlation signal COR0 is also provided to the preamble detection circuit 5. The preamble detection circuit 5 watches the correlation signal COR0 which is indicative of correlation between the spread code and the preamble symbol (the symbol “0”). When the correlation value of the correlation signal COR0 exceeds the predetermined threshold correlation value, the preamble detection circuit 5 generates the detection signal DET for the AND circuit 7. The AND circuit 7 generates the output signal S7 for the timing control circuit 8 in accordance with the detection signal DET. Therefore, the timing control circuit 8 generates the timing control signal TIM for the demodulation circuit 4, based on the detection signal DET, every 32-chips. Meanwhile, since the output signal S7 is provided to the reset-terminal R of the set-reset flip-flop circuit 6, the set-reset flip-flop circuit 6 is reset and then the AND circuit 7 receives a signal of “0. ” Accordingly, the timing control circuit 8 does not receive other detection signals which follow the above-described detection signal DET. That is, the timing control circuit 8 cyclically generates the timing control signals TIM in accordance with the detection signal DET which is first generated from the preamble detection circuit 5. When the demodulation circuit 4 receives the timing control signal TIM, the demodulation circuit 4 selects one of the correlation circuits 3-0 through 3-7 which generates a correlation signal which includes the greatest correlation value which exceeds the predetermined threshold correlation value. Then, the demodulation circuit 4 generates the symbol which corresponds to the correlation signal generated from the selected correlation circuit, as the demodulation signal OUT. Hereupon, when the greatest correlation value of the correlation signal does not exceed the predetermined threshold correlation value, the received signal IN is invalidated and then another signal IN is requested to be sent to the synchronous acquisition circuit. The synchronous acquisition circuit as mentioned above is described in a Document 1 (Japanese Patent Publication Laid-open No. Hei 7-131378).
However, in the above-described synchronous acquisition circuit, when noise causes a signal IN which is similar to the preamble symbol (the symbol “0”) of the spread code to be input to the code generating circuit 2, the preamble detection circuit 5 may erroneously detect the correlation signal COR0 based on the similar signal IN as the preamble symbol. That is, the detection signal DET may be generated from the preamble detection circuit 5 at an improper timing. As a result, the timing control circuit 8 may cyclically generate the timing control signal TIM in accordance with the improper detection signal DET. On such an occasion as this, the spread code as shown in FIG. 1 causes the demodulation circuit 4 to select one of the correlation circuits 3-0 through 3-7 which generates a correlation signal with the greatest correlation value, which exceeds the predetermined threshold correlation value, in accordance with the improper timing control signal TIM. Therefore, even though the synchronous acquisition is not actually realized, the demodulation circuit 4 may generate the demodulation signal OUT every 32-chips. That is, the demodulation circuit 4 may operate as if the synchronous acquisition is realized and then may generate improper demodulation signals OUT.
In order to suppress the improper demodulation signal OUT from being generated, that is, in order to suppress the preamble detection circuit 5 from detecting the correlation signal COR0 at the improper timing, it has been proposed that a detection threshold of the preamble detection circuit 5 is greater than a demodulation threshold of the demodulation circuit 4. As a result, the chance of the improper detection caused by noise may be decreased. However, under poor surroundings of the radio communication, the above-described countermeasure against the thresholds suppresses the desired preamble symbol from being properly detected. That is, the receiver sensitivity may be decreased. Also, when noise is added to the signal IN so that the correlation signal COR0 exceeds the greater detection threshold of the preamble detection circuit 5, it may be still difficult to suppress the improper detection caused by noise in the preamble detection circuit 5.